Single port memory allows either a read or write operation for each cycle time. Typically, the single port memory uses either 6 transistor static memory cells (6 T SRAM) or a single 1-transistor dynamic cell (1T). FIG. 1-A shows a transistor level schematic for the typical 6 T SRAM cell 0. It consists of four NMOS transistors 1,2,5, and 6, and two PMOS transistors 3 and 4. The PMOSs 3 and 4 and NMOSs 5 and 6 configure a CMOS cross-coupled latch, which maintains a data bit as a storage element. The NMOSs 1 and 2 are used to couple the nodes 7 and 8 to the bitlines (BL and bBL) when a wordline WL is activated. This allows the data bit to be read or written from the BL and bBL. FIG. 1-B shows a transistor level schematic for a dynamic memory cell 10. It consists of one NMOS transistor 11 and capacitor 12 (1 T DRAM cell). When a WL is activated, the NMOS 11 couples the capacitor 12 to the BL. This allows a data bit stored in the capacitor 12 to be read or written from BL.
Regardless of the 6 T SRAM or 1 T DRAM, only one WL per array can be activated either for a read or write. This is because activating two or more WLs causes a data contention on the common BL. In order to improve the array utilization, a high performance memory system requires a simultaneous read and write operation.
FIG. 2-A shows a transistor level schematic for a dual port static memory cell. It consists of four NMOS transistors 21, 22, 25 and 26, and two PMOS transistors 3 and 4. Unlike the 1 port SRAM cell, the gates of the NMOS switching transistors, 1A and 1B, couple to different wordlines WL0 and WL1. By activating two word lines, WL0 and WL1, a first memory cell coupling to the WL0 and a second memory cell coupling to the WL1 can be simultaneously read or written through BL0 and BL1 without having a data contention. In accordance with standard usage in the field, the phrase “simultaneously read or written” means ‘during the same clock cycle’. As those skilled in the art are aware, activating WL0 (or WL1) will turn on all the counterpart transistors 21 (or 22) in the row. If the cell to be read and the cell to be written are in the same row, the state of the data will be undefined until the voltages within the cell have stabilized. One of the read and write operations will therefore be delayed according to a convention to avoid contaminating the data. Preferably, the write operation will be done first so that the read operation produces the current data.
FIG. 2B shows a transistor level schematic for a dual port dynamic memory cell. It consists of two NMOS switching transistors 14A and 14B, and one capacitor 16. Similar to the dual port static memory cell, the gates of NMOS switching transistors, 14A and 14B couple to the different wordlines WL0 and WL1. By activating two WL0 and WL1, the memory cell coupling to the WL0 and the memory cell coupling to the WL1 can be simultaneously read or written through BL0 and BL1 without having a data contention.
FIG. 3A shows a transistor level schematic of the 3 T gain cell. The NMOS transistor 34 couples the storage node 32 to the write bitline WBL for a write operation, when the write wordline WWL goes high. The storage node 32 may preferably have a capacitor 35 to store the data bit. The data bit stored in a storage node 32 can be read out to the read bitline RBL when a read wordline RWL goes high. If the storage node 32 contains a high level, two NMOS transistors 31 and 33 are both on, discharging the RBL. If the storage node keeps a low voltage, the NMOS transistor 33 is off, keeping the RBL at the precharged voltage.
FIG. 3-B shows a transistor level schematic for the 2 T gain cell. Similar to the 3 T gain cell, the NMOS transistor 34 couples the storage node 32 to the write bitline WBL for a write operation, when the write wordline WWL goes high. The storage node 32 may preferably have a capacitor 35 to keep the data bit. Unlike the 3 T gain cell, the read NMOS switching transistors 31 are eliminated. The source of the NMOS transistor 32 couples to the read wordline RWL. This thus allows a data bit read operation by measuring a NMOS 33 transistor resistance. A typical method is to apply a voltage between RBL and RWL. They are both high unless they are selected. To read the data bits, RWL goes low. If the data bit is low, the NMOS 33 is off, keeping the RBL at high level. If the data bit is high, the NMOS 33 is on, making the RBL go low. Regardless of the 3 T gain cell or 2 T gain cell discussed above, these cells also allow simultaneous read and write operations.
FIG. 4 shows a memory array architecture for the 3 T gain cell which allows simultaneous read and write operations. A memory 40 consists of an array of 3 T gain cells 42 arranged in a matrix. However, another memory cell, which has a read and write port, may be used. The memory cells are controlled by their corresponding read wordline RWL, write wordline WWL, read bitline RBL, and write bitline WBL. The data bit on the RBL is sensed by the corresponding sense amplifier 43. The WBL is driven by the write driver circuit 44. It is assumed that the memory cells 42A and 42C are in a write mode by activating WWL0, and the memory cells 42B and 42D are in a read mode by activating RWL1, while disabling WWL1 and RWL0. The memory cell data bits in the cells 42B and 42D are read out to the RBL0 and RBL1. They are sensed by the corresponding sense amplifiers 43. A typical sense amplifier utilizes a reference voltage VREF, which allows discrimination between the voltage on the RBL corresponding to the case of reading either a 1 or a 0 from the memory cell. The memory cell data bits in the memory cells 42A and 42C are written through the WBL0 and WBL1. The WBL0 and WBL1 are driven by the corresponding write bitline drivers 44. Note that these read and write operation are simultaneously enabled, which causes a potential RBL and WBL coupling noise.
FIG. 5 shows a simplified RBL and WBL coupling noise model and simulated waveform. It is assumed that the data bit on the RBL1 is being sensed by utilizing the sense amplifier 43, while the adjacent WBL0 and WBL1 are driven by the write drivers 44 for a write mode. It is also assumed that a read bitline RBL1 is precharged to VDD through the PMOS 55. Assuming that the gain cell stores a low data bit, the RBL should maintain VDD. However, when the WBLs go high or low, due to the coupling capacitor between RBL and WBLs, the RBL goes high or low depending on the WBL voltage swing. As shown in a simulation, this coupling noise is as large as 250 mV even if the PMOS load device is not disabled during the sensing operation. Over 250 mV coupling noise makes a simultaneous read and write operation difficult or potentially impossible.
RBL shielding techniques may be used to eliminate this coupling noise. However, this would increase the cell area significantly. Note that this WBL coupling noise to the RBL is a unique problem that results from enabling a simultaneous read and write operation. Note that a conventional BL twisting method is not applicable to cancel the noise, because of a single ended RBL and WBL configuration used in this array.